Users require accurate data storage and retrieval from their peripheral devices. Moreover, they desire being able to accurately store more information on these devices. Various encoding techniques have been developed to increase the data storage density on a peripheral device. The efficiency of these techniques is dependent in part on the accuracy of circuits used for identifying the location and timing of data within the signal. Increasing the accuracy will allow the storage of more information in the peripheral device.
One method of storing data on a disk uses a phase-encoded stream of data, where binary data is encoded into the relative timing between pulses in the signal stream. In this configuration, the data stream comprises overhead and data information. The overhead information is used to identify the location or timing of the data information, with the data information being partitioned into a stream of cells, with each cell representing a bit of data. Each cell is further divided into two detection windows, one of which is assigned a value of "1" and the other being assigned a value of "0". The value of the data bit is determined by the presence or absence of a pulse within these two detection windows of the cell. With a perfect signal (i.e., no noise), one data pulse occurs within each bit cell, either in the early or late detection window.
A decoder digital circuit is generally used to covert the phase-encoded signal into a digital sequence of bits (i.e., 1's and 0's) representing the stored data. A typical decoder performs several functions, including synchronizing the digital pulses in the phase-encoded signal to a precise-frequency digital clock signal; creating a sequence of detection windows; synchronizing the detection windows to the digital data (usually via some kind of synchronization pattern contained in the overhead portion in the digital signal); and converting the phase-encoded data to the binary data bit values based on the pulse locations relative to the detection windows. In addition, the decoder sometimes maintains synchronization between the detection windows and digital data, usually by shifting the time location of the detection windows early or late based on timing of the digital data signal.
In an ideal signal, the data pulses would align exactly with the detection window centers. However it is often the case that this timing is skewed such that a slight but consistent time error exists between data pulses. This scenario occurs in a data signal being derived from magnetic transitions on a disk that is rotating at a speed somewhat different than the design nominal speed. Although the error between any two adjacent pulses might be small, the error will accumulate throughout the phase-encoded pattern such that for longer patterns the error becomes significant. In this situation, the decoder must adapt and synchronize with the data signal to be able to accurately convert the signal into the data.
Commonly, one of several variations of a phase locked loop decoder circuit is used to align the detection windows with the data pulses. Such variations include an analog phase locked loop, a phase encoded data with embedded clock pulses phase locked loop, a self-clocking decode phase locked loop, and a limited response self-clocking decode phase locked loop.
An analog phase locked loop technique can be used to generate the clock signal, where the data pulses are used as the reference input to the phase locked loop.
A phase encoded data with embedded clock pulses phase locked loop adds extra clocking pulses within the data signal, such as adding one clock pulse prior to each data pulse.
A self-clocking decode phase locked loop uses each pulse in the data signal to adjust the start of the window immediately following the pulse. The following detection window is started at some predetermined or fixed time following a data pulse, which allows this method to be very sensitive to noise induced errors, which can cause a dramatic shift in the timing of the detection windows, causing an error in the detection of subsequent bits.
The limited response self-clocking decode phase locked loop, shown in FIG. 1, which compares the timing of each data pulse relative to an "ideal" time which is usually the center of the detection window. If the data pulse is early compared to the ideal time (no measurement is made of how early), then the following detection window is adjusted early by some fixed amount relative to the previous detection window, the adjustment is not made relative to the data pulse timing. Similarly, if the data pulse is late, then the following detection window is adjusted late by some fixed amount relative to the previous detection window. In some implementations, there is a provision for no adjustment if the data pulse is neither early or late, although this requires an odd number of counts per detection window, which may not fit the particular pattern timing and clock frequency choices. The fixed amount of adjustment can be made small (a low number of clock cycles or half-cycles), and thus individual data pulses with high levels of noise (large phase shifts) will not cause large changes in the detection window timing.
However, the limited response self-clocking decode phase locked loop has some deficiencies. This method does provide enough adjustment capability to mitigate any clock frequency error problems in long patterns. However, even when using a minimal detection window adjustment amount (e.g., one or one-half clock cycle) for each early or late data pulse, this method still remains susceptible and sensitive to noise error. This method also does not provide a way to adjust the response of the decoder to the various kinds of errors encountered, and thus it is not possible to optimize the decoder (e.g., minimize the error rate) based on the characteristics of the particular data signal source and noise contained therein.